Si4322
Wake-Up Timer Command
bit
15
1
14
1
13
1
12
0
11
r3
10
r2
9
r1
8
r0
7
m7
6
m6
5
m5
4
m4
3
m3
2
m2
1
m1
0
m0
POR
E196h
The wake-up time period can be calculated by M < m13 : m0 > , R < r3 : r0 > and D < d1 : d0 >:
T wake-up = M * 2 R-D ms
Not e:
The wake-up timer generates interrupts continuously at the programmed interval while the et bit is set.
Extended Wake-Up Timer Command
bit
15
1
14
1
13
0
12
0
11
0
10
0
9
1
8
1
7
d1
6
d0
5
m13
4
m12
3
m11
2
m10
1
m9
0
m8
POR
C300h
These bits can be used for further fine adjustment of the wake-up timer. The explanation of the bits can be found above.
Low Battery Detector and Microcontroller Clock Divider Command
bit
15
1
14
1
13
0
12
0
11
0
10
0
9
1
8
0
7
d2
6
d1
5
d0
4
elfc
3
t3
2
t2
1
t1
0
t0
POR
C213h
The 4-bit value T of t3 - t0 determines the threshold voltage of the threshold voltage V lb of the detector:
V lb = 2.0 V + T * 0.1 V
Bit 4 < elfc >:
Enables low frequency (32 kHz) microcontroller output clock during sleep mode.
Clock divider configuration (valid only if the crystal oscillator is on):
d2
0
0
0
0
1
1
1
1
d1
0
0
1
1
0
0
1
1
d0
0
1
0
1
0
1
0
1
Clock Output
Frequency [MHz]
1
1.25
1.66
2
2.5
3.33
5
10
AFC Command
Bit
15
1
14
1
13
0
12
0
11
0
10
1
9
1
8
0
7
a1
6
a0
5
rl1
4
rl0
3
st
2
fi
1
oe
0
en
POR
C687h
Bit 0 < en>:
Bit 1 < oe >:
Bit 2 < fi >:
Bit 3 < st>:
Enables the calculation of the offset frequency by the AFC circuit (it allows the addition of the content of
the output register to the frequency control word of the PLL).
Enables the output (frequency offset) register
Switches the circuit to high accuracy (fine) mode. In this case the processing time is about four times
longer, but the measurement uncertainty is less than half.
Strobe edge. When st goes to high, the actual latest calculated frequency error is stored into the output
registers of the AFC block.
11
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